Ehsminer – Asic Scrypt Miner 1Gh prototype demo


Dear Litecoiners,

We’ve reached a new stage in our development of mining prototype.

Now, we have a fully- working miner architecture that can be integrated into a complete Asic solution. We have also partnered with a company which can produce a miner in 14nm Silicon.

So, in order to manufacture 1GH mining rigs in 14nm, we have to guarantee an average volume orders at affordable costs. This is considered a huge task to us since we will start leading customers who are able to order to achieve the expected figures.

At the same time, we will also continue to develop new Litecoin architectures based on our acquired experience in ACSMA.

To take full advantage of this situation, we have chosen to work on our design memory especially that we were disappointed several times trying to get IP memories required by this architecture.

This, if realized, can help us make it to the top as we will be able to control power consumption, speed and Silicon area like never before.

Please check back our pages for more updates to come on the current architecture and the future development of ACSMA.

Please note also that all customers interested in the 1GH miner could contact us by filling the form below.

Kindest regards,


Development update 01-04-17

Dear Litecoiners, We have been very busy this past year trying to deliver a low cost, lower power consumption and a very powerful Scrypt miner/mining solution.We had to plan our role in this industry for the long term. This took us to evaluate our current design and make some deep changes.This was due to the fact that the targeted 14nm process we needed to implement lacks of good SRAM solution IPs. We had to start making architecture changes to cope with this reality. 14nm is the only way so far to decrease the energy requirements for solutions in the Giga Hashes, but on the other side, this new technology is very expensive and requires all kinds of compromises. We finally found out that we needed new partners as the companies we worked with in the past had no mature 14nm process offerings . 
Powerful Scrypt miner - Achrix FPGA mining LTC
Scrypt miner: Full SCRYPT algorithm was ported to the FPGA, and now the FPGA is capable of mining any scrypt-based cryptocurrencies
 We now have a good partner capable of delivering what we want and in a short time. We changed the code and started to redevelop a new  and less complex prototype which requires less demanding SRAM. This new IPs can be found ready and will not require additional development cycle. But we believe that our original architecture is a good match for this technology so we carried out development in parallel. 
powerful Scrypt miner: Achronix FPGA Scrypt miner
We are adding stats to the FPGA Scrypt miner to get more verbose runtime logs and output
  We will be giving you more updates in the coming weeks once the manufacture cycle starts. So, please bear with us. This is a very exciting project but also one that requires cutting edge technologies at several aspects including power consumption, cooling, reliability and cost efficiency.We finally take this opportunity to wish you a Happy New Year. 
Ehsminer team

Development update 11-16-15

Acsma is constantly being verified as new functionality is added. Functional verification is done in a multiprocessor system and final verification on a specialized ASIC simulation machine.
Dear Litecoin enthusiasts,
We do apologize for getting this update to you after these few months. As you know time flies, so let us discover what is new about Ehsminer in this newsletter. In the last update, you were given news on the development of our ACSMA Litecoin Miner. Now, after intensive work, we can inform you about what happened along this time.The most important achievement is that we are at the ASIC development stage and we are still committed to carry on the design of our product.
As many of you acknowledge, ACSMA is a very complex architecture with lots of things to tune. It has also several, if not, billions of transistors. The exact number, the chip sizes and many other characteristics will be revealed next time.
The approach taken in the ACSMA architecture is that of the optimization of the use of every electronic resource such as computing units, memory and ultimately every transistor. So, truly enough, in order to prototype such a dense design, we had to abandon the very common technique of using FPGAs to do verification. This requires too much effort because many FPGAs are needed, and more than that the real ASIC libraries are much different. For this reason, we had to retool and start using ASIC emulators which are capable of emulating, in excess of 256 million ASIC gates.
As we now approach the final design stage, we will be updating you on the progress of our enterprise. So, dear Ehsminer fans, stay tuned for more good news in the upcoming days.
Thank you.
Carl Calder ACSMA Project Manager

Development update 03-31-15

The Cadence Palladium 3
A special Hardware Emulator delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification
 We have been working very hard on the development of ACSMA, our ultra-optimized Scrypt mining architecture. This work is carried out at our ASIC development facility in Denver Colorado USA.In order to test this very dense logic design several steps have been taken.
Step 1: Test of Reduced Number of Blocs being mined in a simplified version of ACSMA.
This first step required two phases:1) A simulation of a simplified version of ACSMA is tested thoroughly on a PC server in order to verify the functioning of the complete mining process, configuration and communication.2) The Logic Synthesis, this is the process of converting high level language used to create ACSMA into hardware primitives like gates memory, FIFOs, registers etc. This is to analyze resources requirement and FPGA verification using an ACHRONIX testbed, for demo purposes.
Step 2: Test of Full version of ACSMA with Reduced Number of Scrypt defined ROMMIX units (this is because of memory requirements).
This second step required two phases:3) A simulation of mining process is tested on a PC server. Once again this is to verify the full functioning of the mining process of a large scale ACSMA unit.4) The logic Synthesis and FPGA verification are also used to analyze logic resources using a dual XILINX-ACHRONIX testbed.This is to showcase our product.We have been working at all these points concurrently. We can only show now results of point 1 and point 2.We have our demo of point 3 which is almost ready and will be shown pretty soon.Once point 4 is finished and exposed, ASIC preparation can start with our ASIC partner.So we will keep you posted as things are taking shape now.Best RegardsEhsminer Team


Development update 12-25-14

FTDI Communication Interface has been re-designed and tested correctly
Our high speed communication Interface has been re-designed and tested correctly
We are pleased to announce that our communication USB 2.0 high speed interface is fully working now. It was designed to be compatible with the upcoming USB 3.0 new FTDI chip. This interface will allow a maximum of 480Mb/s delivered to the mining rig in version 2.0. around 8 times more faster in USB 3.0 version. This is really a huge number even with OS overhead that is more efficient to the achievement of the payload delivery. Now we are in the process of putting together the final proof of concept. A Raspberry Pi Linux system will be used as a Host Miner (for the demo only). CPUMiner 0.8 has been adapted to feed ACSMA. We have gained new knowledge in the Scrypt algorithm and will introduce few changes in ACSMA that will potentially make it a game changer. For reasons of privacy, we can not disclose anything at this point. You need only to male sure that parallel design of the architecture is always going on.So Merry Christmas and Happy New Year.Kindest Regards,Ehsminer Team

Development update 12-08-14

FTDI interface
We are busy trying to remove all the bugs in our design. So the code can be handed over to an ASIC partner. Many people start asking for big mining rigs. That is why, we had to redesign the communication interface.
 This represents a lot of communication bandwidth by using a new host USB 3.0 which is in the making by a supplier FTDI from the UK. It will be probably be available by mid of next year.We enterprise to design an interface that will be compatible with that new part which is also compatible with the signal level we needed in our Asic chips.For now, we have to use level shifters and this is proves to be awkward to deal with these configurations of 200 chips or more. Finally, we are in the process of testing the new level adapters and we hope to have this section working soon.Kindest Regards,Ehsminer Team

Development update 11-17-14

ACSMA testWe are aware that a lot of people are waiting for our proof of work design. Although the functional verification in simulation was done long time ago, we have incurred in several delays in the FPGA port.Last week we discovered that we were experiencing a lot of noise in the communication interface. This came from the fact that this interface is high speed and it is supposed to support in excess of 200 asic chips. But the real problem was in the Achronix verification platform. Their development tools had a bug and we were confronted with only one option to synchronize the external high speed clock of the communication interface with the communication module inside the FPGA. This created so much noise, so we started to get a corrupted data. It was only yesterday that it was made clear that our communication interface has been properly designed and we can now continue our tests of the ACSMA architecture .
We will be showing side by side simulation results as well as the data process being inside the FPGA port of ACSMA.
Once again we will ask you to please bear a little more with us.
Best Regards,Ehsminer Team


Development update 11-03-14

 The  ACSMA architecture has become very complex and it has been quite a challenge to devise an efficient testing mechanism. Therefore, we decided to speed up the design validation to read the results of different modules as computation progresses throughout the unit. Then, we compared them to the pure RTL simulation.For this reason, we modified the communication interface in order to transfer big data streams to upload them to a host computer .This implies a communication test interface that uses most of the USB bandwidth. At this stage we suffered a set back last week when the signal quality of the main communication clock source was incompatible with the test platform. We tried different approaches as suggested by Achronix support. Although this product is new; there were several inconsistencies that made us take other approaches, as our main goal is not a FPGA port of the ACSMA, but a validation of the design to be ported to an ASIC solution. We want to clarify an important aspect. As we explained in our last post  “Development update 10-17-14” that the hash rate number can be only a power of two.So please bear with us, as we are laying the foundation for a highly optimized technological solutions for cryptocurrencies. Best regards,Ehsminer Team

Development update 10-17-14

Update on ACSMA testing:

Parallella 16
The Parallella board with its Epiphany-III 16-core 65nm Microprocessor/coprocessor will be used as a host miner
The development of an ASIC is a dynamic process. It requires compromises of price, power, heat and silicon area. This decision is taken while evaluating and testing of the design in the FPGA prototyping phase.We had only to do a minor change in one of the modules of ACSMA, and this requires to minimize the amount of blocks of RAM we were using, since Nfactor algorithms in ACSMA require memory sizes that must be a power of 2. However, in our ACSMA architecture , Litecoin can use some other sizes. While the memory reduction was only 5%, it led us to modify several things and then simulate the behavior with a true cycle simulation tool.We are now in the process of routing the design and starting to test it in the FPGA evaluation platform by adjusting it to new changes. A new logic analyzer module has been added to follow the Hashing computation in real time.This design in a simplified form approaches now 4 millions equivalent gates and  200K lines of hardware description language code.It is important to produce a highly optimized architecture, as this will lessen heat production and power consumption which are considered as key elements of the design.Kindest RegardsEhsminer Team

Development update 10-03-14

Good News :

Dear Miners, we wanted to give you a quick update on the progress of work. Be assertive, everything is running well. Here is the advancement of work:
  • The high speed USB communication between the host machine and the Achronix platform required a logic translator. This was prototyped and is currently being tested.
  •  The port of the Multithreaded miner is capable of 4000 Communication Threads (not processing), was debugged and it is now capable of start sending work to the ACSMA unit through USB connection.
  •  ACSMA unit was modified to communicate with the “Communications Multithreaded Miner Host Application”
The pieces work by themselves and now the whole system is going to be integrated as a whole unit for proof of concept.Kindest RegardsEhsminer Team